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A frequency modulation control loop is designed with proportional-integral control. Sampled-data modeling is used to derive the necessary transfer functions to build the control loop. A primarily test chip is fabricated in 28-nm FDSOI technology to evaluate the design.
a) To ensure a completely coordinated design, the pad-mounted capacitor bank shall be constructed in accordance with the minimum construction specifications required to provide adequate electrical clearances and adequate space for operation of the unit and any required handling of components. Specifications must be verified by factory.
So far, most of the control of the capacitor voltage of sub-module is based on the capacitor voltage sorting method and is implemented in combination with the modulation algorithm.
Parasitic series inductance of the wires of MOM capacitor leads to frequency dispersion of capacitance and resonance effect. At frequencies higher than the resonant frequency = 1 / LC, the capacitor behaves as an inductor (inductive impedance dominates over capacitive impedance).
Under the traditional balancing control, the range of the sub-module capacitor voltage's fluctuation is (232, 260 V). Under the optimised balancing control, the range of the voltage's fluctuation is (218, 270 V). Therefore, the authors can see that the fluctuation of the voltage under optimised balancing control is greater.
More possibilities for bonding pad's capacitance reduction in case of MOS with serial p-n capacity, can be provided by using a reverse-bias voltage (Urb), applied to isolated zone, under the bonding pad. Ordinary, similar solution is used in bipolar technology devices for the purpose of electrical isolation by p-n junctions.
F3D can also generate a compact device model for MOM capacitors that can be used for efficient circuit simulation. These models have a limited number of elements and allow describing frequency-dependent characteristics of MOM capacitors. III.
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